A typical MRAM structure includes a simple 1-transistor and 1-magnetic tunnel junction (MTJ) memory cell. The MTJ is formed between metal (Mx) layers, e.g., Mx and Mx+1, and the state of a bit is detected as a change in resistance.
Such an approach for forming a MTJ is illustrated in FIG. 1. Adverting to FIG. 1, metal layer 101, e.g., Mx, is formed in interlayer dielectric (ILD) 103. A metal cap 105 is then formed over the metal layer 101 and ILD 103. Next, a bottom electrode (BE) dielectric 107 is formed over the metal cap 105. Thereafter, a BE electrode 109 is formed over the metal layer 101. A MTJ 111 is then formed between the BE electrode 109 and a top electrode (TE) 113. Next, a passivation layer 115 is formed over edges of the MTJ 111 and the TE 113, and over the BE 109. Thereafter, a tetraethyl orthosilicate (TEOS) layer 117 is formed over the passivation layer 115 and the metal cap 105. A metal layer etch stop layer 119 and a metal layer 121, e.g., Mx+1, are then formed over the TEOS layer 117 and the TE 113. Further, a TEOS layer 123 is formed over the metal layer 121 and the metal layer etch stop layer 119. The described process flow requires three (3) different lithography masks to fabricate, which are costly and time consuming in terms of wafer processing.
A need therefore exists for methodology enabling fabrication of a self-aligned MTJ without using lithography masks and the resulting device.